The phenomenal growth exhibited by the semiconductor industry over the past three decades has been due in large part to the ability of manufacturers to provide a 25-30% per year cost reduction per function throughout this period. Design innovation, device architecture ‘shrinks’, wafer size increases, and yield improvement have been some of the factors enabling this remarkable performance. According to the 1997 Edition of the National Technology Roadmap for Semiconductors (NTRS), published by the Semiconductor Industry Association, the largest contribution to productivity growth over the next three device generations will be decreased feature size; this dimensional scaling increases the packing density of transistors per square centimeter in an integrated circuit.
Complexity of integrated circuits and resulting manufacturing challenges escalate as feature sizes decrease. Use of conventional materials technologies and design approaches arm projected to increase manufacturing complexity to the point where the costs of fabrication or deleterious effects on yield and reliability offset the benefits of dimensional scaling.
Among the most significant factors in determining device size and chip performance for the next technology generations, with transistor gate sizes starting at approximately 180 nm and diminishing to sub-100 nm widths, are the structures and materials employed for signal transmission to and from the active device regions. Globally referred to as ‘interconnect’, these processes already represent more than half the fabrication process budget for leading-edge microprocessors. Interconnect architecture improvements now rank among the most intense areas of semiconductor process and integration development, and are anticipated to remain so for the foreseeable future.
One of the enhancements to interconnect structures anticipated to see rapid adoption is the replacement of aluminum and tungsten signal transmission lines by lower-resistance copper. In a departure from conventional practice, where metals are typically vacuum deposited by sputtering or heterogeneous vapor/solid biphase reactions, copper interconnect will likely be introduced using electroplating or electrochemical deposition (ECD) processes, which feasibility studies have shown to be well matched to the demands of Damascene processes, the processes that have now been adopted by the microelectronic fabrication industry to form copper interconnects.
Though electroplating has long been employed as a fundamental step in fabrication of multilevel printed circuit boards, application of electroplating to fill sub-micron interconnect features is relatively recent and poses further additional problems, including the need for more stringent control of electroplating bath composition.
Electroplating is a complex process involving multiple ingredients in the plating bath. It is important that the concentration of several of the ingredients be kept within close tolerances in order to obtain a high quality deposit. In some cases, chemical analysis of individual solution constituents can be made regularly (such as pH measurement for acid content), and additions made as required. However, other addition agents such as brighteners, leveling agents, suppressants, etc., together with impurities, cannot be individually analyzed on an economical or timely basis by a commercial plating shop. Their operating concentration is low and their quantitative analysis is complicated and subject to error.
When using an electroplating bath, the ability to monitor and control bath composition is a key factor in ensuring uniform and reproducible deposit properties. In semiconductor and microelectronic component applications, the electronic and morphological properties of the copper films are of principal importance in determining final device performance and reliability. The stability of later processes in the Damascene patterning flow depend on repeatable mechanical properties including modulus, ductility, hardness, and surface texture. All of these deposit properties are controlled or strongly influenced by the composition of the electroplating bath.
Of particular importance is measurement and control of proprietary organic compounds which serve to modify the deposit properties through adsorption onto and desorption from the cathode surface during plating, affecting the diffusion rate of copper cations to nucleation and growth sites. These compounds are typically delivered as multi-component packages from plating chemistry vendors. One of the most important functions of the additive packages is to influence the throwing power of the electroplating bath: the relative insensitivity of plating rate to variations in cathodic current density across the wafer or in the vicinity of surface irregularities. The throwing power of the electrolyte has a major effect on the cross-wafer uniformity of plated film thickness and the success with which ultrafine trenches and vias (holes) are filled without included seams or voids. Organic additives have also been shown to have dramatic effects on mechanical film properties. Detection and quantification of these important bath constituents is complicated by the fact that they are effective at very low concentrations in the electrolyte, at several ppm or less.
Plating bath analysis for microelectronic applications is strongly driven by the need to limit variability and maintain device yields through maintenance of optimized process parameters. One method for controlling such ingredients in an electroplating bath is to make regular additions of particular ingredients based upon empirical rules established by experience. However, depletion of particular ingredients is not always constant with time or with bath use. Consequently, the concentration of the ingredients is not actually known and the level in the bath eventually diminishes or increases to a level where it is out of the acceptable range tolerance. If the additive content goes too far out of range, the quality of the metal deposit suffers and the deposit may be dull in appearance and/or brittle or powdery in structure. Other possible consequences include low throwing power and/or plating folds with bad leveling.
A common method for evaluating the quality of an electroplating bath is disclosed in Tench U.S. Pat. No. 4,132,605 (hereafter the Tench patent). In accordance with the procedures of the Tench patent, the potential of a working electrode 10 is swept through a voltammetric cycle, including a metal plating range and a metal stripping range, for at least two baths of known plating quality and an additional bath whose quality or concentration of brightener is to be evaluated. The integrated or peak current utilized during the metal stripping range is correlated with the quality of the bath of known quality. The integrated or peak current utilized to strip the metal in the bath of unknown quality is compared to the correlation and its quality evaluated. In a preferred embodiment of said patent, the potential of an inert working electrode 10 is swept by a function generator through the voltammetric cycle. An auxiliary electrode 20 immersed in the plating bath is coupled in series with a function generator and a coulometer to measure the charge from the working electrode 10 during the stripping portion of the cycle.
An improvement to the method disclosed in the Tench patent is described by Tench and White, in the J. Electrochem. Soc., “Electrochemical Science and Technology”, April, 1985, pp. 831-834 (hereafter the Tench publication). In accordance with the Tench publication, contaminant buildup in the copper plating bath affects the copper deposition rate and thus interferes with brightener analysis. The Tench publication teaches that rather than continuous sweep cycle utilized in the above-referenced patent, a method be used involving sequentially pulsing the electrode between appropriate metal plating, metal stripping, cleaning, and equilibrium potentials whereby the electrode surface is maintained in a clean and reproducible state. Stated otherwise, where the process of the Tench patent involves a continuous voltammetric sweep between about −600 mV and +1,000 mV versus a working electrode and back over a period of about 1 minute, the Tench publication pulses the potential, for example at −250 mV for 2 seconds to plate, +200 mV for a time sufficient to strip, +1,600 mV to clean for seconds, +425 mV for 5 seconds to equilibrate, all potentials referenced to a saturated Calomel electrode, after which the cycle is repeated until the difference between successive results are within a predetermined value, for example, within 2% of one another.
The procedure of the Tench publication provides some improvement over the procedure of the Tench patent, but during continuous use of an electroplating bath and following successive analysis, contaminants build up on the electrodes and analysis sensitivity is lost. Further, as the present inventor has found, such procedures frequently fail when applied to certain used baths. The inability to accurately measure additive concentrations in such used baths effectively reduces the life time of the bath and increases the cost associated with producing, for example, semiconductor integrated circuits and microelectronic components.